ECSS-Q-ST-70-12C Rev.1

ECSS PCB Insulation Clearance Calculator

Compute as-designed and as-manufactured insulation distances for rigid, flex, and sculptured flex PCBs per ECSS-Q-ST-70-12C Rev.1 (30 April 2025). All five geometric cases of Figure 13-1, with full normative traceability.

Figure 13-1: Five geometric cases of insulation distance
Figure 13‑1. ECSS-Q-ST-70-12C Rev.1: the five geometric cases of insulation distance

Input Parameters

Rigid = T13-7, standard FR4 multilayer, 0 to 500V. Flex = T13-8, polyimide-based flex PCB or the flex section of a rigid-flex, 0 to 150V (above 150V: not covered by this standard). Sculptured Flex = T13-9, single-layer flex with trapezoidal copper section (§8.7), 0 to 150V, only XY internal clearance is specified (no Z, no external, no holes).
Enter the worst-case peak transient voltage between the two conductors (§13.8.2b). This is not the nominal working voltage or RMS. Include transients, surge, and failure-mode voltage if required by the project. If one net is GND (0V), enter the peak voltage of the other net. Range depends on PCB type: rigid 0 to 500V, flex and sculptured flex 0 to 150V. Above the upper bound requires specific qualification (§13.8.2l); flex above 150 V is not covered by ECSS-Q-ST-70-12C.
Worst-case peak transient voltage (§13.8.2b)
Total copper thickness in µm, base foil plus plating. The T13-7 tolerance categories are defined on total Cu per T7-3, whose columns are literally "Basic Cu / Plated Cu / Total Cu thickness"; §7.4.2c excludes only planarization, copper reduction and surface preparation from the total, and its NOTE 2 states "the plated copper thickness as-designed is 25 µm" per plating step. Typical totals: 17 (unplated), 35, 42 (17+25), 60 (35+25), 67 (17+2×25), 70, 85 (35+2×25), 95 (70+25) µm. Thicker copper means larger etching tolerance, hence larger as-designed clearance. Above 95 µm there is no T13-7 category (Cu ≥ 105 µm is a heat sink, §10.4.2a). Fine pitch: basic foil ≤ 17 µm (§7.4.3f); on internal layers without plating steps, so total = basic ≤ 17 µm (§7.4.5g); on external layers plating is allowed (fine pitch column covers Th ≤ 70 µm).
µm. Total Cu: base + plated (T7-3)
Normal = standard track and pad spacing. Fine = denser spacing, used only for impedance-controlled routing or signal routing to AAD (§7.4.5c). Fine pitch on internal layers is limited to ≤30V (§7.4.5d), requires Cu ≤17µm without plating (§7.4.5g), and must be recorded as Review Item (§7.4.5b). Fine pitch is incompatible with reliable insulation (§13.9.3.1 NOTE 9). On flex, fine pitch on external terminations is not permitted (T13-8).
Whether the external layer has conformal coating, potting, or encapsulation (§13.8.4g). Mandatory for: fine pitch external (§13.8.4b), any voltage >30V on external layers of rigid PCB (§13.8.4c, Paschen discharge risk at launch), reliable insulation on external layers (§13.9.3.2a). On flex terminations T13-8 tabulates explicit uncoated values up to 150V for normal pitch. Selecting "Without" above 30V on rigid returns NOT PERMITTED, except for connector pad footprints where coating cannot penetrate between pins (§13.8.4d).
Standard = minimum clearance for all net pairs (T13-3 rigid, T13-4 flex). Reliable §13.9 = increased clearance for critical nets (§13.9.2a): unprotected main bus power, Single Point Failure nets, nets whose insulation loss would propagate failure to another critical net, cross-strapped functions. Reliable is determined by the functional role of the net, not by its voltage. A 5V SPF net requires reliable insulation, a 400V non-critical net does not. FAI (First Article Inspection) is mandatory when reliable insulation is applied (§13.9.2d).
Affects only Case 5 (hole-to-hole). Determines the registration tolerance added to as-designed values (§13.8.2i NOTE). Single = one lamination cycle, ±100µm tolerance. Standard rigid PCBs. Sequential = multiple lamination cycles (build-up, HDI), ±300µm. Rigid-flex = also ±300µm. The bond sequence is determined by the PCB manufacturer at the time of drilling (§13.10d), not by the designer, but the designer must know the build-up to select correctly. On flex, hole-to-hole clearance is not tabulated separately in T13-8; T13-7 Part 4 values are applied.
None = standard PCB, no HDI exceptions apply. Select an HDI option only for sequential build-up constructions with laser microvias. A board that merely USES polyimide as laminate material (e.g. all-polyimide rigid multilayer with mechanical blind/through vias) is NOT HDI: select None — base material does not change T13-7 clearances. HDI build-up, microvia (§11.4) = build-up layers containing microvias (blind vias <250µm, laser-drilled). Z min reduced to 60µm (§11.4.1h); above 30V superimposed conductors are not permitted (§11.4.1j). HDI build-up, polyimide dielectric (§11.6) = complete HDI technology per Table 11-1 (1.0mm pitch AAD). Clearance reduced to 63/70µm for 0 to 10V fine pitch. Max 2 microvia layers per side, staggered. Reduced pad §7.5.3l = internal pad diameter reduced with annular ring ≥25µm (instead of 50µm). Requires teardrop reinforcement, wicking conformance, electrical registration coupon, and Review Item. All HDI options are Review Items in the PCB definition dossier. HDI options apply to rigid PCBs only.

Enter parameters and click Calculate
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Disclaimer: This tool is provided by BlackIoT Sagl as a free reference utility and comes with no warranty of any kind. BlackIoT Sagl assumes no responsibility for the accuracy, completeness, or suitability of the computed values. It is the sole responsibility of the user to verify all results against the original standard ECSS-Q-ST-70-12C Rev.1 (30 April 2025) before use in any design or procurement decision. This tool is not an official ESA or ECSS publication.